CertusPro-NX N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation

Aggregation up to 8 channel Image Data

The majority of image sensors and application processors (AP) in the consumer market use the Mobile Industry Processor Interface (MIPI®) Camera Serial Interface 2 (CSI-2) as a video signal interface. In some cases, the AP has to take multiple image data for various applications without increasing the physical interface signals.

The Lattice Semiconductor N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation reference design for CertusPro™-NX devices offers up to eight-channel aggregation. Multiple channel image data are concatenated horizontally line by line. CertusPro-NX has two MIPI hard macro IPs, which can be used as MIPI TX or RX module (D-PHY Hard IP). The RX module can also be realized by a soft macro utilizing general DDR modules (D-PHY Soft IP).

Features

  • Two to eight Soft RX channels can be aggregated
  • All RX channels must be in the same configuration
  • Maximum RX bandwidth is 1.5 Gb/s per lane
  • Maximum TX bandwidth is 1.5 Gb/s per lane
  • Number of TX lanes can be one, two, or four
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N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation with CertusPro-NX Block Diagram

Documentation

Technical Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
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CertusPro-NX N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation – Source Code​
1.0 3/15/2022 ZIP 85.2 MB
CertusPro-NX N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation – User Guide
FPGA-RD-02253 1.3 10/15/2024 PDF 1.6 MB

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