The high-speed PRNG from Xiphera is a Pseudorandom Number Generator (PRNG) Intellectual Property (IP) core. The IP core is based on Counter (CTR) operation mode of a 256-bit Advanced Encryption Standard (AES) and uses a high-speed AES-CTR implementation as an integral building block.
Versatility: The IP core supports the forward prediction resistance mode, which can be set on and off between output generation, as well as the use of personalization strings and additional inputs for instantiation and reseeding.
Standard Compliance: The high-speed PRNG IP core is compliant with the NIST SP800-90A specification. The IP core can be combined with Xiphera's NIST SP800-90B compliant balanced TRNG to form a NIST SP800-90C compliant Random Bit Generator (RBG).
High Performance: The IP core can achieve over 16.18 Gbps throughput, while consuming only about 36855 4-input Lookup Tables (4LUTs) in a typical Lattice ® FPGA implementation.
Easy integration with AXI4-lite and AXI stream interface.