The Lattice Video Scaler IP core is used to scale up or scale down the resolution of a video stream. The IP supports scaling from an arbitrary input resolution to a wide range of output resolutions as configured by the user. Its flexible architecture supports a wide variety of scaling algorithms. The highly configurable design takes advantage of the embedded RAM and DSP blocks available in Lattice FPGAs. A simple I/O handshake makes the core suitable for either streaming video or burst input video data. In-system input and output frame size update is possible on a frame basis.
The design is implemented in Verilog HDL. It can be configured, generated and implemented using the Lattice Radiant Software. It supports CertusPro™-NX, Certus™-NX, and CrossLink™-NX FPGA devices.
Supports Four Scaling Algorithms – The IP supports four scaling algorithms namely, nearest neighborhood, bilinear interpolation, bicubic interpolation, and multi-tap Lanczos filter. The Lanczos filter supports multiple taps from 4 to 12. Filter coefficients are generated at compile time when the kernel is configured.
Scaling Factors for the Horizontal and Vertical Dimensions – The Video Scaler IP core allows different scaling factors for the horizontal and vertical dimensions. It performs vertical and horizontal scaling in two steps.