AHB-Lite to AXI4 Bridge Module IP Core

Interface Between AHB-Lite Manager and AXI4 Subordinate

Related Products

The Lattice Semiconductor AHB-Lite to AXI4 Bridge provides an interface between a single high speed AHB-Lite manager (compliant to AMBA 3 AHB-Lite Protocol Specification) and a AXI4 subordinate (compliant to AMBA AXI and ACE Protocol Specification Version H.c).

Resource Utilization details are available in the IP Core User Guide.

Features

  • AHB-Lite to AXI4 conversion supports configurable data bus width: 8, 16, 32, 64, 128, 256, 512, and 1024 bits.
  • AHB-Lite to AXI4-Lite conversion supports configurable data bus width: 32, 64 bits.
  • Supports configurable address width: 11 to 32 bits.
  • Supports configurable AXI4 ID bus width (1 to 11 bits) so that the width can be matched with the subordinate ID bus width, but the ID value for this bridge is always tied to 0 since AHB-Lite does not have the concept of ID.

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Block Diagram

AHB-Lite to AXI4 Bridge IP Core Block DiagramExpand Image

Ordering Information

The AHB-Lite to AXI4 Bridge IP is provided at no additional cost with Lattice Propel Builder.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
AHB-Lite to AXI4 Bridge IP Module - User Guide
FPGA-IPUG-02242 1.5 6/26/2026 PDF 1 MB

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