AHB-Lite to AXI4 Bridge Module IP Core

Interface Between AHB-Lite Manager and AXI4 Subordinate

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The Lattice Semiconductor AHB-Lite to AXI4 Bridge provides an interface between a single high speed AHB-Lite manager (compliant to AMBA 3 AHB-Lite Protocol Specification) and a AXI4 subordinate (compliant to AMBA AXI and ACE Protocol Specification Version H.c).

Resource Utilization details are available in the IP Core User Guide.

Features

  • Supports configurable data bus width: 8, 16, 32, 64, 128, 256, 512, and 1024 bits
  • Supports configurable address width: 11 to 32 bits
  • Supports configurable AXI4 ID bus width (1 to 11 bits) so that the width can be matched with subordinate’s ID bus width, but the ID value for this bridge will be always tied to 0 since AHB-Lite does not have the concept of ID.
  • Supports basic and burst transfer. Single and indefinite length increment transfer on AHB-Lite are converted to INCR burst with length=0 on AXI4.
  • Supports narrow transfer where the requested transfer size can be less than data bus width.

Jump to

Block Diagram

AHB-Lite to AXI4 Bridge IP Core Block Diagram放大图片

Ordering Information

The AHB-Lite to AXI4 Bridge IP is provided at no additional cost with Lattice Propel Builder.

Documentation

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AHB-Lite to AXI4 Bridge IP User Guide
FPGA-IPUG-02242 1.4 12/11/2025 PDF 874.2 KB

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