AHB-Lite to AXI4 Bridge IP Core

Interface Between AHB-Lite Manager and AXI4 Subordinate

The Lattice Semiconductor AHB-Lite to AXI4 Bridge provides an interface between a single high speed AHB-Lite manager (compliant to AMBA 3 AHB-Lite Protocol Specification) and a AXI4 subordinate (compliant to AMBA AXI and ACE Protocol Specification Version H.c).

The design is implemented in Verilog HDL. It can be configured and generated using the Lattice Propel Software and implemented within Lattice Radiant software. It supports CertusPro™-NX and Lattice Avant™-NX FPGA devices.

Supports Basic and Burst Transfer – Single and indefinite length increment transfer on AHB are converted to INCR burst with length=0 on AXI.

Supports Configurable AXI4 ID Bus Width (1 to 11 bits) – Support is for the width to be matched with subordinate’s ID bus width, but the ID value for this bridge will be always tied to 0 since AHB does not have the concept of ID.

Features

  • Supports configurable data bus width: 8, 16, 32, 64, 128, 256, 512, and 1024 bits.
  • Supports configurable address width: 11 to 32 bits.
  • Supports narrow transfer where the requested transfer size can be less than data bus.
  • Supports write/read data bus pipeline for relaxing timing critical path.
  • Supports Secure Access at AXI interface.

Jump to

Block Diagram

Resource Utilization

Lattice Avant Devices
Attribute Values Clock Fmax (MHz) LUTs Register EBRs
Data Width AXI Timeout Counter Read Data bus Pipeline Enable Write Data bus Pipeline Enable Narrow Transfer Support
32 0 0 0 0 350 95 82 0
32 0 1 1 0 350 89 144 0
32 128 0 0 0 350 118 108 0
32 128 1 1 0 350 115 180 0
256 0 0 0 0 350 95 82 0
256 0 1 1 0 350 97 604 0
256 128 0 0 0 350 118 108 0
256 128 1 1 0 350 122 620 0
32 0 0 0 1 350 105 96 0
32 0 1 1 1 350 106 161 0
32 128 0 0 1 350 128 115 0
32 128 1 1 1 350 125 170 0
256 0 0 0 1 350 125 116 1
256 0 1 1 1 350 128 634 1
256 128 0 0 1 350 150 139 1
256 128 1 1 1 350 156 652 1

Notes:
1. Address width is always set to 32 bits in all configurations listed.
2. The resource values are populated using LAV-AT-E70-1LFG676C device compiled in the Lattice Radiant 2023.1 design software with Synplify Pro. When the IP is combined with other blocks in the FPGA, the value can be expected to vary from the value in the table.

Lattice CertusPro-NX Devices
Attribute Values Performance Grade = 7 & 8_Low-Power Performance Grade = 9_Low-Power and all High-Performance grade LUTs Register EBRs
Data Width AXI Timeout Counter Read Data bus Pipeline Enable Write Data bus Pipeline Enable Narrow Transfer Support
32 0 0 0 0 160 200 83
87
0
32 0 1 1 0 160 200 83 151 0
32 128 0 0 0 160 200 109 105 0
32 128 1 1 0 160 200 104 169 0
256 0 0 0 0 160 200 83
87 0
256 0 1 1 0 160 200 86
599
0
256 128 0 0 0 160 200 109 105 0
256 128 1 1 0 160 200 104 617 0
32 0 0 0 1 160 200 94
94 0
32 0 1 1 1 160 200 94
158 0
32 128 0 0 1 160 200 115 112 0
32 128 1 1 1 160 200 115 176 0
256 0 0 0 1 160 200 116 118 2
256 0 1 1 1 160 200 116 630 2
256 128 0 0 1 160 200 137 136 2
256 128 1 1 1 160 200 137 648 2

Notes:
1. Address width is always set to 32 bits in all configurations listed.
2. The resource values are populated using LFCPNX-50-7ASG256C & LFCPNX-50-9ASG256C device compiled in Lattice Radiant 2023.1 design software with Synplify Pro. When the IP is combined with other blocks in FPGA, the value can be expected to vary from the value in the table.

Ordering Information

The AHB-Lite to AXI4 Bridge IP is provided at no additional cost with Lattice Propel Builder.

Documentation

快速参考
标题 编号 版本 日期 格式 文件大小
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AHB-Lite to AXI4 Bridge IP Core - User Guide
FPGA-IPUG-02242 1.0 12/5/2023 PDF 852.9 KB