​​JESD204B IP Core​

​​Supports Both the JESD204B Tx and Rx Directions with Corresponding Multiple Layers on Lattice FPGAs​

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​​JESD204B is a high-speed serial interface used between data converters, such as analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), and the FPGA device to replace traditional interfaces, such as CMOS and LVDS. With converter sampling rates and data throughput increasing, the JESD204B interface offers advantages in terms of size, cost, and speed.

JESD204B for Lattice Radiant – CertusPro-NX
JESD204B for Lattice Diamond – ECP5-5G, ECP5 and LatticeECP3.

Resource Utilization details are available in the IP Core User Guide.​

Features

  • ​​JESD204B subclass 0 and 1.​
  • ​​​​Lane rates up to 8.192 Gb/s for CertusPro-NX devices.​
  • ​​​​Configurable lane counts of 1, 2, or 4 lanes.​
  • ​​​​Scrambler and descrambler.​
  • ​​​​SYSREF modes: One-shot and Periodic (always).​

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Block Diagram

JESD204B IP Block DiagramExpand Image

Resource Utilization

Nexus Device

Resource Utilization on LFCPNX-100 LFG672 Device
IP Configuration JEDS204B IP LUT4 Logic LUT4 Ripple Logic PFU Registers EBR
Mode = Rx_and_Tx
Number of Lanes = 4
Scrambling = Enabled
Number of Octets per Frame (F) = 4
Number of Frames per Multiframe (K) = 32
Transport Layer Enable = Unchecked		 RX Link Wrapper 3551 526 5358 4
TX Link Wrapper 3445 610 3223 0
TX and RX PHY Wrapper 373 40 480 0
Mode = Rx_and_Tx
Number of Lanes = 4
Scrambling = Enabled
Number of Octets per Frame (F) = 4
Number of Frames per Multiframe (K) = 32
Transport Layer Enable = Checked		 RX Link Wrapper 2406 526 4376 4
RX Transport Wrapper 30 0 83 1
TX Link Wrapper 3440 610 3219 0
TX Transport Wrapper 136 0 286 4
TX and RX PHY Wrapper 372 40 480 0


Legacy Devices

LatticeECP3-70 Utilization (JESD204B 3G)
IP User-Configurable Parameters Slices LUTs Registers sysMEM EBRs
F=3, L=2 ,K=9, Subclass1, Scram=0, Rx 2828 4886 2174 2
F=3, L=2 ,K=9, Subclass1, Scram=0, Tx 354 651 266 0

Note: Performance and utilization data target an LFE3-70EA-6FN672C device using Lattice Diamond 3.2 and Synplify Pro I-2013.09L software. Performance may vary when using a different software version or targeting a different device density or speed grade.

LFE5UM-85 Utilization (JESD204B 3G)
IP User-Configurable Parameters Slices LUTs Registers sysMEM EBRs
F=3, L=2 ,K=9, Subclass1, Scram=0, Rx 1826 2276 2170 2
F=3, L=2 ,K=9, Subclass1, Scram=0, Tx 289 534 266 0

Note: Performance and utilization data target an LFE5UM-85F-8BG756C device using Lattice Diamond 3.2 and Synplify Pro I2013.09L software. Performance may vary when using a different software version or targeting a different device density or speed.

Ordering Information

  Part Number
Device Family Multi-site Perpetual Single Seat Annual
CertusPro-NX JESD-204B-CPNX-UT JESD-204B-CPNX-US
ECP5-5G JESD-204B-E5G-UT JESD-204B-E5G-US
ECP5 JESD-204B-E5-UT JESD-204B-E5-US
LatticeECP3 JESD-204B-E3-UT1 JESD-204B-E3-US

An IP core-specific license is required to enable full, unrestricted use of the JESD204B IP core in a complete, top- level design. You can get the license after the IP is purchased.

To find out how to purchase the JESD204B IP core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
JESD204B IP Core – Lattice Radiant Software
FPGA-IPUG-02259 1.0 6/28/2024 PDF 2.5 MB
JESD204B IP Core – Lattice Diamond Software
FPGA-IPUG-02010 2.3 6/20/2017 PDF 3 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
JESD204B IP Core - Release Notes​
FPGA-RN-02006 1.0 6/28/2024 PDF 181.2 KB

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