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FPGA design constraints - performance and analysis to achieve design and timing closure

FPGA Design Constraints – Performance and Analysis to Achieve Design and Timing Closure
Posted 12/15/2021 by Roger Do, Senior Product Manager, Design Tools, Lattice Semiconductor

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Traditionally, FPGA design was simple. Designers set a basic clock constraint that was propagated across the chip. But now, FPGA designs have become much more complex. There are multiple clocks, and relationships between those clocks. There may be clock domain crossings that need to be accounted for. So, FPGA design tools today must feature much greater analysis capabilities to show the designer, for example, where those clock domain crossings are, to be able to constrain for multiple clocks, and to constrain at the I/Os to make sure that you can get on and off chip.

Constraints are used to guide FPGA design implementation tools such as synthesis and place-and-route functions. They allow the design team to specify the performance requirements of the design and to help the tools to meet those requirements. Design constraints and timing constraints are important in FPGA design because they not only tell the tools what to optimize, but also tell the tools what to report on. A design that is unconstrained will go unoptimized and unreported, because no constraints have been set to tell it how fast it needs to run; also, the tools won’t tell you how fast the design is performing because there was no instruction to say that such information was required.

Therefore, in the latest release of Lattice's Radiant design tool, we have focused on two goals - performance and analysis.

Figure 1: Radiant 3.1
Figure 1: Radiant 3.1

Radiant 3.1 improves the correlation between the timing constraint and the timing analysis so that the simulated performance is as close a fit to that of the actual device performance as possible. This release of the design tool also continues the progress we've been making in terms of clock frequency. Over this last year, on average, systems have seen a 10% increase in maximum frequency (Fmax) as well as a 15% reduction in runtime.

But to really know whether your design will achieve the required performance, you need more 'what if' type analysis - especially at the I/Os so that getting on and off chip is more easily understood. Radiant 3.1 includes a standalone timing analysis tool and a differential I/O 'eye diagram' monitor showing the transition from low to high, so designers can see how big the opening is. Designers can fine tune the SerDes settings to optimize the 'eye' opening to optimize the operating window.

Fig 2: 'Eye' opening monitor for CertusPro-NX SerDes I/O
Figure 2: 'Eye' opening monitor for CertusPro-NX SerDes I/O

Ease of use

One of the advantages that Lattice tools enjoy is that because Lattice is focused on smaller FPGAs - up to 100,000 LUTs in Radiant - the tools can be much more streamlined when compared to Xilinx Vivado or Altera Quartus that must also support multi-million LUT devices. So, Lattice tools are faster to download, faster to install and often quicker to implement than competing solutions. Today, we have a push-button execution where we read in the code, do the optimization, and produce a result. As Lattice moves up into larger densities, we’ll continue to refine our hierarchical block-based design to support team-based designs. Starting in Radiant 3.1, we've added a virtual IO capability which facilitates block design and macro creation allowing for performance and utilization estimates without having to map internal signals to external I/O pins.

Complexity of design is not going to go away, so design tools should be simple and intuitive to use. Our tools are the easiest to use in the FPGA world. Our tools guide designers through the process using a lot of wizards, and we employ graphical constraining methods in our tools that make the constraint management easier. The way we report out is also simple - especially with the standalone timing analysis - we provide a spreadsheet of everything that’s going on.

Different levels of reference design - from simple demos to specific applications, for example, implementing a PCIE interface, and then onto the Lattice solution stacks that take the designer through, perhaps, a machine learning video sensor type of application that may incorporate multiple IPs and different design effects - also make it easier for designers to work with FPGAs.

Figure 3: Stand-alone timing analysis report
Figure 3: Stand-alone timing analysis report

Lattice also offers 'strategies' for getting the best performance, the lowest area, and the lowest power. These are strategy settings in Radiant that direct how the tools behave, adjusting different synthesis options, different mapping options and different place-and-route choices.

Radiant provides a trusted IP ecosystem. As well employing a user interface that is very easy to use and intuitive, the Radiant environment employs industry-leading third-party tools, such as Synopsys' Synplify™ Pro synthesis tool and ModelSim™ from Mentor Graphics/Siemens for verification, that are very familiar - everyone uses them.

Finally, in addition to the extensive security measures featured in in Lattice FPGAs, all the Radiant tools are digitally signed and delivered to ensure that no one has tampered with them.

Radiant has been optimized to deliver predictable convergence with advanced optimization for fast, efficient timing closure using powerful, accurate analysis and debugging tools.