Lattice Edge AI and FPGA Solutions

The Lattice Nexus 2 small FPGA platform provides advanced connectivity, optimized power and performance, and leading security.

The Lattice Nexus small FPGA platform enables low power, high reliability, and high performance design.

The Lattice Avant mid-range FPGA platform features class leading 25 Gbps SERDES, hardened PCIe^® and external memory PHY interfaces.

The Lattice Avant-E FPGA features high logic density, abundant DSPs, ample embedded memory, and LPDDR4 support, enabling low-latency, power-efficient AI processing ideal for real-time edge applications like vision, robotics, and industrial automation.

The Lattice CertusPro-NX FPGA is optimized for edge AI applications, featuring up to 100k logic cells, ample on-chip memory, up to 156 DSPs, and low power consumption, while supporting LPDDR4, PCIe Gen3, and 10G SERDES, making it ideal for real-time, parallel processing near sensors with minimal latency.

The Lattice CrossLink-NX FPGA is built for edge AI applications, offering up to 40k logic cells, high memory-to-logic ratio, and low power consumption, with hardened or software MIPI D-PHY support, PCIe or USB 3.2 interfaces options, making it ideal for embedded vision and AI inferencing.

The Lattice iCE40 UltraPlus is perfect for very low power edge AI applications, featuring up to 5280 LUTs, ultra-low static current (75 µA), and soft neural network IPs, enabling always-on intelligence with efficient pattern matching and AI inferencing.

The Lattice sensAI solution stack accelerates the integration of flexible, low power inferencing at the edge. It provides everything needed to evaluate, develop, and deploy FPGA-based machine learning and AI solutions.

The Lattice sensAI Studio is a streamlined, user-friendly development environment for effortlessly deploying machine learning models onto Lattice's low power FPGA platforms. With Lattice sensAI Studio, developers can train, optimize, and deploy AI models using pre-trained assets or their own datasets, specifically targeting Lattice FPGAs.

The Lattice sensAI Edge Vision Engine empowers developers with advanced AI and machine learning capabilities, featuring sophisticated computer vision functionalities and a camera viewer for effective visualization. It accelerates development by enabling quick integration of computer vision and audio AI on Lattice hardware and general-purpose processors.

The Lattice Design Group brings our team’s unmatched experience on Lattice products, software, and solutions to solve your application challenge.

Lattice Semiconductor and NVIDIA have developed an edge AI solution that simplifies and accelerates the deployment of intelligent edge systems by enabling rapid design of connectivity bridging applications from sensor to compute. The Sensor Bridge Reference design, implemented on the CertusPro-NX Sensor to Ethernet Bridge Board, seamlessly integrates with Nvidia Holoscan Sensor Bridge, offering programmable system control, configurable FPGA IP, and a full stack solution for data acquisition and processing, along with a standard API supporting various interfaces and protocols.

In this talk, we explore the transformative power of FPGAs in edge computing. We discuss how FPGAs enable real-time data processing, enhance IoT devices, and revolutionize industries like autonomous vehicles and smart manufacturing and dive into innovative use cases that leverage the low power, low latency, and flexibility of FPGAs, unlocking new possibilities for an intelligent edge.

In this demo, users can explore the latest tools from Lattice, with the ability to run examples for FPGA simulation, neural network training, and device-specific compilation.

This demo processes radar, lidar, and camera sensors simultaneously, showcasing the fused data processing among the sensors in real time. It demonstrates the flexibility of I/O and the computing power to handle multiple sensors and machine learning (ML). Sensor data (camera, radar, pressure) is pre-processed by the FPGA and sent to the CPU (Raspberry Pi) over PCIe. The CPU controls the robot arm and sends position info back to the FPGA, which generates commands for the arm.