LatticeECP3 I/O Protocol Evaluation Board

The LatticeECP3 IO Protocol Evaluation Board provides a convenient platform to evaluate, test and debug user designs and IP cores targeted for the LatticeECP3 FPGA. The LatticeECP3 I/Os are connected to a rich variety of both generic and application-specific interfaces.

Some common uses for the LatticeECP3 IO Protocol Evaluation board include:

  • Applications requiring large DDR3 memory width and depth
  • High-speed parallel ADC/DAC Interface
  • SERDES data transfer with external devices
  • 1000base-T PHY/RJ45 networking
  • A single-board computer system
  • A platform for evaluating the Input/Output (I/O) characteristics of the FPGA
  • A platform for evaluation and development with Lattice IP cores

ADC-DAC Interface Card

The ADC-DAC interface card connects to the HMZD connector on the IO protocol board, and has two connectors that match ADC and DAC boards from TI.

Features

  • SPI Serial Flash device included for low-cost, non-volatile LatticeECP3 configuration storage
  • Two 64-bit DDR3 DIMM module sockets
  • Tri-speed (10/100/1000 Mbit) Ethernet PHY with RJ-45 (includes 12 core magnetics)
  • USB 2.0 transceiver
  • Built-in USB 2.0 download for LatticeECP3 and ispPAC® bitstreams.
  • Also includes ispDOWNLOAD™ JTAG headers for LatticeECP3, ispPAC, and MachXO™ bitstreams
  • High-speed HMZD connector with 80 differential pair connections and selectable VTT voltage
  • 8-pin DIP switch and three user-definable debounced pushbuttons
  • Discrete LEDs and 7-segment LED
  • LCD module connector
  • Prototyping areas with 125 spare test point I/O pins
  • 1 selectable user I/O bank voltage with access to 2 VREF test points
  • Logic analyzer probe connection
  • 5 pairs of high-speed differential I/O using SMA connectors
  • 5 crystal oscillators
  • 2 selectable high-speed differential external clock sources with PLL feed back inputs
  • 4 channels (1 quad) of differential SERDES (TX and RX) using SMA connectors
  • 1 high-current high-speed I/O connection using an SMA connector
  • 3.3V, 2.5V, 1.5V, 1.2V and DDR3 voltages are generated from a single 12V power source
  • 3 fixed or adjustable DDR3 reference voltages
  • 1 Mbit serial EEPROM for general data storage over I2C bus
  • Power Manager II ispPAC-POWR1220AT8 chip for monitoring input power and regulator outputs to be within nominal tolerance with programmable trims
  • ispVM™ System programming support
  • Multi-board JTAG programming capability and sysCONFIG™ connector

Jump to

Board Photos

10 LatticeECP3 IO Protocol Evaluation Board Bottom ViewExpand Image

Bottom View

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10 LatticeECP3 IO Protocol Evaluation Board Top ViewExpand Image

Top View

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ADC-DAC Interface CardExpand Image

ADC-DAC Interface card

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I/O Board With ADC-DAC Interface CardExpand Image

I/O Protocol Board With ADC-DAC Interface card

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Ordering Information

  • LatticeECP3 IO Protocol Board: LFE3-150EA-IO-EVN
  • ADC-DAC Interface Card: LFE3-ADC-DAC-EVN
  • Click here to find an authorized Lattice distributor near you
  • Click here to order now from the Lattice Online Store

Documentation

Quick Reference
Information Resources
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
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Parallel Flash Programming and FPGA Configuration
Also download the implementation files for AN8077. 		AN8077 1.3 3/1/2015 PDF 2.4 MB
Parallel Flash Programming and FPGA Configuration - Source Code
For use with Application Note - AN8077 		AN8077 1.3 1/4/2013 RAR 1.4 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Parallel Flash Programming and FPGA Configuration
Also download the implementation files for AN8077. 		AN8077 1.3 3/1/2015 PDF 2.4 MB
Parallel Flash Programming and FPGA Configuration - Source Code
For use with Application Note - AN8077 		AN8077 1.3 1/4/2013 RAR 1.4 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
LatticeECP3 DDR3 Demo for the LatticeECP3 I/O Protocol Board User's Guide
UG38 01.4 6/8/2012 PDF 2.7 MB
LatticeECP3 I/O Protocol Board to Texas Instruments ADC/DAC Adapter Board
EB54 1.3 12/4/2014 PDF 3 MB
LatticeECP3 PCI Express Root Complex Lite x1 Native Demo
UG40 1.0 10/29/2010 PDF 263.2 KB
LatticeECP3 I/O Protocol Board - Revision C User's Guide
EB48 01.4 3/23/2012 PDF 6.1 MB
Programming Cable - User Guide
Describes the features and recommended usage guidelines of Lattice ispDOWNLOAD Cables. 		FPGA-UG-02042 26.7 4/24/2024 PDF 992.6 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Wireless Solutions Brochure
I0197 3.0 8/14/2012 PDF 2 MB
Lattice HetNet Solutions Brochure
I0234 1.0 11/12/2013 PDF 2.2 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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GEN2 Serial RapidIO and Low Cost, Low Power FPGAs
1.0 8/4/2011 PDF 276 KB
Implementing PCI Express Bridging Solutions in an FPGA
1.0 7/1/2010 PDF 970.1 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
LatticeECP3 PCI Express Root Complex Lite x1 Native Demo
1.0 11/1/2010 ZIP 2.7 MB
LatticeECP3 DDR3 Demo
1.4 6/8/2012 ZIP 235.3 KB
ECP3 IO Protocol Board (IOPB) Default Programming Files
1.2 3/25/2011 ZIP 186.6 KB

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