Fast Page Mode DRAM Controller

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Reference Design LogoFast page mode DRAM offers improved speed over standard DRAM. When memory access is performed within the same address row (page), a single precharge is required for only the first access. Subsequent access within the page can then be made without the time penalty of additional precharge cycles. Although it has lost popularity in some areas to faster technologies such as double data rate (DDR) SDRAM, FPM DRAM is still a very cost-effective solution when the highest performance is not required.

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Block Diagram

Performance and Size

Tested Devices* Language Performance I/O Pins Design Size Revision
LCMXO2-1200HC-6TG144CES Verilog >200MHz 47 56 LUTs 2.3
LCMXO2-1200HC-6TG144CES VHDL >200MHz 47 55 LUTs 2.3
LC4256ZE-5TN100C Verilog >165MHz 47 42 Macrocells 2.3
LC4256ZE-5TN100C VHDL >165MHz 47 43 Macrocells 2.3
M4A3-128/64-55VC Verilog >90MHz 47 42 Macrocells 2.3
M4A3-128/64-55VC VHDL >90MHz 47 43 Macrocells 2.3
ispLSI5128VE-180LT128 Verilog >100MHz 47 42 Macrocells 2.3
ispLSI5128VE-180LT128 VHDL >100MHz 47 43 Macrocells 2.3
LCMXO256E-5T100C Verilog >200MHz 47 55 LUTs 2.3
LCMXO256E-5T100C VHDL >200MHz 47 55 LUTs 2.3
LFXP2-5E-5M132C Verilog >200MHz 47 56 LUTs 2.3
LFXP2-5E-5M132C VHDL >200MHz 47 55 LUTs 2.3

* May work in other devices as well.

Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.


Technical Resources
Fast Page Mode SDRAM Controller - Documentation
FPGA-RD-02090 2.4 1/22/2021 PDF 887.1 KB
Fast Page Mode SDRAM Controller - Source Code
RD1014 2.3 11/8/2010 ZIP 110.4 KB

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