The high-throughput AES256-GCM from Xiphera implements the Advanced Encryption Standard (AES) in Galois Counter Mode (GCM). AES-GCM is a widely used cryptographic algorithm for Authenticated Enryption with Associated Data (AEAD) purposes, as it provides both data confidentiality and authenticity.
Performance: The IP core achieves a throughput in the Gbps range, for example 15.92+ Gbps in Lattice ECP5.
Standard Compliance: The IP core is fully compliant with both the Advanced Encryption Algorithm (AES) standard and the Galois Counter Mode (GCM) standard.
Moderate Resource Requirements: The entire IP core requires 49516 Lookup Tables (4LUTs) (Lattice® ECP5®), and does not require any multipliers, DSPBlocks or internal memory in a typical Lattice FPGA implementation.
Features
- 128-bit and 256-bit Interfaces ease the integration of the high-speed AES-GCM with other high-speed FPGA logic.
- Optimized Implementation utilising unrolling, pipelining, optimized AES S-box design, and GMAC calculation based on pipelined Karatsuba multipliers enable extremely high performance.
