EP550: SD / SDIO / MMC Host Controller

The EP550 is a host controller for SD memory card, SDIO and MMC interface. The core connects the host CPU of the system to the SD card socket. External SD cards can be accessed by the host CPU through the EP550 controller core IP.

SD memory and SDIO are low cost, high speed interfaces designed for removable mass storage and IO devices. It is a very flexible architecture supporting variable clock rate from 0 to 25Mhz and data width of 1 to 4 bits. A data rate of up to 12.5Mbyte/sec (100Mbs) can be realized with SD interface. Features such as plug and play, auto-detection, error correction, write protection are standard with SD card interface.

The EP550 SD card host controller core is designed according to the SD Association's SD host controller specification. The core presents a very simple view of the SD card to the system software. All access to the SD card are made through the standard control register set. DMA, burst access, CRC error detection, interrupt, timing, etc. are supported by the controller core. Because of the standard register set, the EP550 can be used to replace other existing SD controllers with no change to system software.

There are several options for user hardware interface to the controller core. The controller supports generic user interface optimized for on-chip logic interface as well as embedded CPU interface such as AMBA AHB bus. To access the SD card, the host CPU simply issue read/write access to the control registers in the core. The controllers core handles all the SD card protocol automatically including data shifting, timing and CRC generation. The core has a built-in DMA controller so that data can be automatically transferred between the system and the SD card without CPU intervention.

With the EP550, SD card interface can be realized with very little development cost. Designer can add SD memory and SDIO interface to the system by simply adding the EP550 module without changing the rest of the system architecture.


  • Host controller for SDIO, SD memory card, and MMC interface.
  • Allows host CPU to access SD, SDHC and MMC devices.
  • Simple user interface optimized for on-chip bus connection.
  • User interface supports 32-bit and 64-bit data.
  • Wishbone compatible interface.
  • Option to integrate with other CPU bus slaves to support direct access by various CPU's including PowerPC, MPC860, ARM, SH2/3/4, MIPS, and ARC microprocessors.
  • Supports SDIO DMA operation for high speed data transfer.
  • Supports SD host controller standard register set.
  • Fully programmable access timing.
  • Hardware support of CRC error detection and interrupt generation.
  • Supports multi-function SD cards, command suspend, resume, and block transfers.
  • Option to operate the user interface and card interface at different clock domains.
  • Designed for ASIC and PLD implementations.
  • Fully static design with edge triggered flip-flops.Supports up to 4 banks of NAND Flash devices.

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Block Diagram

Performance and Size

The following are typical performance and utilization results.

Lattice Device Utilization Performance
Slices Percentage
LFEC6 1719 56 78
LFE2-50E 1771 7 118
LFE2M-50E 1771 7 101
LFXP10C 1719 35 45
LFXP2-17E 1771 21 90
LFSC3GA15E 1779 23 152

Ordering Information

This IP core is supported and sold by Eureka Technology, contact Eureka Technology at info@eurekatech.com or visit their website at www.eurekatech.com for more information.


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Eureka: EP550 SD / SDIO / MMC Host Controller
4/7/2008 PDF 97.7 KB

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