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PCI Express Demos for the ECP5 PCI Express Development Board User’s Guide

Using a web browser, go to the ECP5 PCI Express Board Setup (Windows) page, and download the Windows setup.exe file: DK-ECP5-PCIE-setup.exe. 2. Double-click on the DK-ECP5-PCIE-setup.exe file. 3. If the Install Program as Other User dialog appears, choose to install as the…

Document

PCI Express Demos for the ECP5 and ECP5-5G Versa Development Board User Guide

User Manual FPGA-UG-02006 1.5 PDF 0.8MB

Document

ECP5 PCI Express Development Kit Quick Start Guide

To run the PCI Express Basic Demo, go to C:\Lattice_DevKits\KD-ECP5-PCIE-010\ Demonstration\PCIeBasic\, run PCIeBasic. bat. 2. The 14-Segment Control window in the demo allows interactive control of the LEDs display on the board.

Board

ECP5 Evaluation Board

Evaluation and development for ECP5-5G FPGA - 85K LUTs. Includes generous IO access and easy expansion to PMOD, Arduino, RaspberryPI, SERDES interface and more

Board

ECP5 Versa Development Kit

Evaluate and develop for key connectivity features of the ECP5 FPGA, including PCI Express, Gigabit Ethernet, DDR3 and generic SERDES, includes numerous demos.

Webpage

ECP5 / ECP5-5G

With a focus on compact, high volume applications, Lattice optimized ECP5 for low cost, small form factor and low power consumption. These characteristics make ECP5 ideal for delivering programmable connectivity to complement ASICs and ASSPs.

Board

ECP5 PCI Express Development Kit

No longer available - for reference only. Enables rapid evaluation of PCI Express technology on low cost ECP5 FPGA platform.

Webpage

Part Number Reference - ECP5 Family

Get the part number description/reference guide for the ECP5 family here.

FAQ

ECP5/ECP5-5G: What is the tolerable amount of overshoot/undershoot for ECP5 I/Os?

ECP5 I/Os operates at VCCIOmax of 3.465V with an additional overshoot/undershoot tolerance of +/-180mV for junction temperature at 100degC and +/- 100mV for junction temperature of 125degC without reliability hazard.

Reference Design

7:1 LVDS Video Interface for MachXO2/3 and ECP5

Implements standard 7:1 LVDS interfaces using the FPGA I/O structure

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Lattice Semiconductor Enables Rapid Prototyping of Smart Connectivity Designs with ECP5 Versa Development Kit

Promotional Offer Now Available for New ECP5™ Versa Development Kit and Lattice Diamond® Software

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Lattice Breaks the Rules with ECP5 FPGA Family for High-Volume Small-Cell, Microserver, Broadband Access & Video Applications

New family combines 40% lower-cost, 30% lower power and 2X functional density in the smallest package to meet the unique needs of fast growing high-volume markets

FAQ

Lattice ECP5 : What is the VSSIO used for in the pinout file of ECP5?

Description:The VSSIO is the system ground or the ground reference voltage pin of the I/O pins. You can connect the VSSIO to the GND pin.

FAQ

IO for ECP5/ECP5-5G\u200B: Does ECP5 have a dedicated reset IO?

ECP5 can utilize any GPIO as reset on their design, In order to utilize a dedicated routing for the reset, users may use the GSR (Global Set/Reset IO) resource. The primitive can be utilized either through inference or design instantiation. If it is utilized through inference, the tool will…

FAQ

ECP5/ECP5-5G: What is ECP5 AES Key Serialization mean in technical level?

Lattice is following the AES Standard (FIPS197) for Key Serialization in ECP5.

FAQ

ECP5: Does the ECP5 IBIS model support Keysight's ADS tool?

Yes, the device supports Keysight's ADS for the ECP5 IBIS model.

Webpage

Lattice ECP5 Family Adoption Grows as New Member Delivers Unprecedented Performance in the Smallest Package

Over 100 early access customers already in progress with Lattice Diamond design tool, development boards, soft IP and reference designs

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Lattice’s Low Power, Small Form Factor ECP5 FPGA Enables Ximmerse VR/AR Tracking Platform

PORTLAND, OR – Sept. 26, 2017 – Lattice Semiconductor Corporation (NASDAQ: LSCC), the leading provider of customizable smart connectivity solutions, today announced that Guangdong Virtual Reality Technology Co., Ltd. (Ximmerse), a provider of interaction systems for mobile AR/VR applications, has…

FAQ

Platform Manager: How to add a Real Time Clock (RTC) with a Fault Logger for ECP5 using Platform Manager 2?

Description:This article describes adding Real Time Clock (RTC) with a Fault Logger for ECP5 using Platform Manager 2.Solution:The Full-Featured Fault Logger Configuration for ECP5 has several additional features for Timestamp. One of these is the "Externally Assigned Time Stamp"…

FAQ

Diamond ECP5: Is it possible to program the LFE5U-85F-8BG381C into an ECP5 Evaluation Board that has LFE5UM5G-85F-8BG381C with a free license?

No, you cannot. The free license cannot be used with LFE5UM5G-85F-8BG381C on the board. Please contact sales for the Diamond license pricing or order through our Online Store.Contact Sales: https://www.latticesemi.com/en/Buy/SalesLocator Online Store:…