N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation with CertusPro-NX

Aggregation up to 8 channel Image Data

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The majority of image sensors and application processors (AP) in the consumer market use the Mobile Industry Processor Interface (MIPI®) Camera Serial Interface 2 (CSI-2) as a video signal interface. In some cases, the AP has to take multiple image data for various applications without increasing the physical interface signals.

Using the N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation reference design for CertusPro™-NX devices offers up to eight-channel aggregation. Multiple channel image data are concatenated horizontally line by line. CertusPro-NX has two MIPI hard macro IPs, which can be used as MIPI TX or RX module (D-PHY Hard IP). The RX module can also be realized by a soft macro utilizing general DDR modules (D-PHY Soft IP).

Non-continuous clock mode - Used to write the data to RX FIFO and the continuous byte clock is used to read the data from RX FIFO.

Horizontal Pixel - All RX channels are expected to have almost same frame timing (20-pixel timing or less).

Lane Aligner Module - Enabled in case of Soft D-PHY in 2-lane and 4-lane configurations.

Features

  • Two to eight Soft RX channels can be aggregated
  • All RX channels must be in the same configuration
  • Maximum RX bandwidth is 1.5 Gbps per lane
  • Maximum TX bandwidth is 2.5 Gbps per lane
  • Number of TX lanes can be one, two, or four
Lattice mVision Solutions Stack

Block Diagram

Documentation

技术资源
标题 编号 版本 日期 格式 文件大小
选择全部
N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation with CertusPro-NX - Source Code
1.0 3/15/2022 ZIP 85.2 MB
N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation with CertusPro-NX - Documentation
FPGA-RD-02253 1.0 3/15/2022 PDF 1.7 MB
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