Internal Reference: For the MachXO2 EFB (Embedded Functional Block), the Primary I2C cannot be used to access both on-chip Flash and User Logic in the same design. Is there a workaround to use the Primary I2C of the MachXO2 EFB to access both CFG (Configuration) and User Logic in a design at the same time?
This is not a recommended I2C configuration. We recommend to use primary I2C for configuration logic and secondary I2C
for user logic. However, there is a workaround to
use the same bus of the primary I2C to access both configuration and
user logic.
1. Out-of-band dynamic disable, or external control pin
with normal RST (Reset) signal to EFB(Embedded Functional Block) State Machine. The external system asserts pin
when CFG/UFM (User Flash Memory) is to be accessed, and releases prior to resuming user access.
This requires one extra device pin.
We can generate one control signal, such as
config_in_process, which indicates if UFB/Configuration is in
process. Then \u201Cor\u201D the normal RST and config_in_process, the output is
used to drive the reset of the EFB module, that is wb_rst_i.
2. In band,
one-time permanent disable: Use an in-band command recognized by the
internal user WB state machine to disable itself. Use the command before
in-field CFG upgrade. REFRESH restores the entire FPGA function. This does not require
extra device pin.
Before UFB/Configuration, the I2C master should
send this command first. Only an external event (for example, REFRESH or RST or
timer time-out) will restart the WB state machine.