Article Details

ID: 1958
Case Type: faq
Category: Architecture
Related To: PLL/DLL/Clock Routing
Family: LatticeECP3

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How do I find the locations of a preferred PLL and its dedicated clock input pin in a LatticeECP3 device?

In a LatticeECP3 device each dedicated clock input pin is paired to specific PLL. This pairing occurs in a form of a dedicated connection between the clock input pin to that PLL. If a user want to use a PLL directly from a clock input pin, he or she is strongly recommended to use the correct pairing by using location constraints on both the clock input pin and the PLL location. Failure to do so could result in a less than optimal routing and excessive delays between clock input pin and the PLL.

To find the PLL location and the clock input pins, you will need two documents that can be found in Lattice's website.

The first document is the "LatticeECP3 sysCLOCK PLL/DLL Design and Usage Guide" (TN1178). 

The second document is the pinout spreadsheet of your device, which can be found in the following link.

For the second link, you will need to search for the "pinout" spreadsheet of your device (e.g. ECP3-17EA, ECP3-70E, etc).

First, in the "PLL/DLL Design and Usage Guide", there is a table (Table 10-17) that lists all of PLL locations and the preferred pads for each PLL. Here, you will need to search for your device and find the desired PLL location (column 2). After finding the desired location, see which pad is the preferred pads for your desired PLL location. Next you will need to find the pin name of the preferred pad in the "pinout" spreadsheet. This is the summary of the process to find the pair of PLL and its preferred pins' names. You can also use this process in reverse (i.e. from pin names to the PLL location).

As an example, let's suppose that your device is an LFE-70E with FPBGA484 package type, and that your clock input pin into the device is pin "K6". So the first document that you want to use is the LatticeECP3-70E Pinout. For ease of reading, please open the pinout's .csv file using Microsoft Excel.

In the .csv, locate the column labeled "FPBGA484". Under that column, find pin "K6". For this specific pin, you will find the "Pin/Ball" column entry to be "PL43E_D". Note this entry and now open the PLL/DLL Design and Usage Guide (TN1178).


In TN1178, go to Table 10-17 and find the sub-entry for "LatticeECP3-70/95". This is where information for LFE-70E device is located. Now find the "Pin/Ball" entry that you noted earlier (i.e. "PL43E_D"). From this information locate the PLL location by looking at the entry in second column of the row that has your "Pin/Ball" entry. This is the preferred PLL (i.e. "PLL_R43C5") for the dedicated clock input that you selected.

In short, from the example above, given the pin name "K6", the preferred PLL location is "PLL_R43C5".