TSEMAC & SGMII Reference Design

Implements 1G/100M/10M Ethernet Application using a TSEMAC with SGMII PCS IP Core

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This reference design demonstrates an example of 1G/100M/10M Ethernet application using a TSEMAC IP Core with a SGMII PCS IP Core in loopback mode. A simple Ethernet packet generator is included to generate ethernet packets to be transmitted on Tx and compare them with received packets from Rx.

TSEMAC IP Core - Transmits and receives data between a client application and an Ethernet network. The main function of the Ethernet MAC is to ensure that the Media Access rules specified in the IEEE 802.3 standard are met, while transmitting and receiving Ethernet frames.

SGMII/Gb Ethernet PCS IP Core - The SGMII PCS Core provides GMII interface to MAC and follows the Ethernet frame standard. It converts GMII frames into 8-bit code groups in both transmit and receive directions and performs auto-negotiation with a link partner as described in the Cisco SGMII and IEEE 802.3z specifications. SGMII IP is a connection bus for MACs and PHYs and is often used in bridging applications and/or PHY implementations. It is particularly widely used as an interface for a discrete Ethernet PHY chip.


  • Tri-Speed Ethernet Media Access Controller (TSEMAC):
    • Compliant to IEEE 802.3-2005 standard
    • Full- and half-duplex operation in 10/100 mode
    • Host control interface configurable to either APB, AHB-Lite, or AXI4-Lite
  • Serial Gigabit Media Independent Interface (SGMII):
    • PCS functions for IEEE 802.3z (1000BASE-X)
    • Dynamic selection of SGMII/1000BASE-X PCS operation
    • Easy Connect option for seamless integration with Lattice Semiconductor's Tri-Speed Ethernet MAC (TSMAC) IP core
  • Ethernet packet generator to generate and compare packets
  • Supports operation speeds of 1 Gbps, 100 Mbps and 10 Mbps
  • Devices including CertusPro-NX and CrossLink-NX are supported

Block Diagram

Resource Utilization

Device Family Language Speed Grade Utilization (LUTs) fMAX (MHz) I/O Architecture Resources
CertusPro™-NX1 Verilog -9 3492 >125 17 1 PLLs, 1 ECLKDIV
CrossLink™-NX1 Verilog -8 3490 >125 15 1 PLLs, 1 ECLKDIV

1. Performance and utilization characteristics are generated using LFCPNX-100-9LFG672C and LIFCL-40-8BG400C with the Lattice Radiant™ software version 2023.2 and Lattice Synthesis Engine (LSE).

Note: Note: The maximum clock frequency is obtained by running the timing analysis with the Lattice design software. Timing simulation must run after any changes are made and the reference design is merged with the overall design.


Technical Resources
Select All
CrossLink-NX TSEMAC & SGMII Reference Design - Source Code
1/29/2024 ZIP 2.8 MB
TSEMAC & SGMII Reference Design - User Guide
FPGA-RD-02271 1.2 1/29/2024 PDF 4.9 MB
CertusPro-NX TSEMAC & SGMII Reference Design - Source Code
1/29/2024 ZIP 2.8 MB

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