The Lattice Semiconductor Tri-Speed Ethernet Media Access Control (TSEMAC) IP core supports the ability to transmit and receive data between a host processor and an Ethernet network. The main function of the TSEMAC IP core is to make sure that the media access rules specified in the IEEE 802.3 standards are met while transmitting a frame of data over the Ethernet. On the receive side, the TSEMAC IP core extracts the different components of a frame and transfers them to higher applications through an AXI4-Stream interface. The SGMII PCS IP core provides GMII interface to the MAC and follows the Ethernet frame standard. It supports 8-bit of data and 8-bit of control signals for both transmit and receive path.
This reference design demonstrates an example of 1G/100M/10M Ethernet application using a TSEMAC IP core with a SGMII PCS IP core in loopback mode. A simple Ethernet packet generator is included to generate Ethernet packets to be transmitted on the transmitter (TX) and compare them with the received packets from the receiver (RX).
Features
- Tri-Speed Ethernet Media Access Controller (TSEMAC):
- Compliant to IEEE 802.3-2005 standard
- Full- and half-duplex operation in 10/100 mode
- Host control interface configurable to either APB, AHB-Lite, or AXI4-Lite
- Serial Gigabit Media Independent Interface (SGMII):
- PCS functions for IEEE 802.3z (1000BASE-X)
- Dynamic selection of SGMII/1000BASE-X PCS operation
- Easy Connect option for seamless integration with Lattice Semiconductor's Tri-Speed Ethernet MAC (TSMAC) IP core
- Ethernet packet generator to generate and compare packets
- Supports operation speeds of 1 Gbps, 100 Mbps and 10 Mbps
- Devices including CertusPro-NX and CrossLink-NX are supported
