Lattice Sentry 2.2 BKC Reference Design

Basic Framework for PFR Design Implementation

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The Lattice Sentry Best-Known Configuration (BKC) Reference Design provides a basic framework to implement a PFR design. It instantiates needed IP and provides examples of driving GPIO and communicating between the firmware and logic.

This reference design provides the hardware guidelines/signal and interconnection checklist for customers implementing the Intel® Eagle Stream Compatible PFR (Platform Firmware Resiliency) and General Processor Compatible PFR based on the Lattice Semiconductor Mach™-NX device and AMI® Tektagon™ XFR.

Signal Interconnection between PRoT, FCH, PCH, BMC, and CPU – The PFR design is created using a Lattice Propel™ workspace. The workspace consists of IP components, software, and hardware design files. The IP components exist in either the Mach-NX SoC Function Block (SFB) or are instanced in the User FPGA logic (FPGA) as indicated below. FPGA IP is managed through the Propel Builder tool. The software is AMI's Tektagon XFR firmware, which runs on a RISC-V processor located in the SFB. The hardware design files are managed in Lattice Diamond® software.


  • Dual and Single Flash memory architectures
  • Optional DICE and SPDM support to provide PRoT Attestation
  • Functionality escalation and customization using additional Lattice IP’s
  • Flexible design to support Intel Eagle Stream and General Processor based platforms
  • Mach-NX device implementing PFR to protect BMC and BIOS Firmware and Control PLD

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