HyperRAM Memory Controller Reference Design

Enabling the CrossLink™-NX Device to Interface with HyperRAM Devices

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The HyperRAM controller is designed to enable the CrossLink™-NX device to interface with HyperRAM devices that uses the HyperBus interface. It provides you with two separate standard interfaces (AXI-4) for sending write and read commands to the HyperRAM devices, as well as for accessing the Control Registers of the design.

The HyperRAM Controller provides two AXI-4 access ports, which are composed of a Memory Control Port to access the HyperRAM, and a Register Control Port to access the control registers of the HyperRAM Controller. The Memory Control Port supports AXI-4 protocols with burst-based transactions and the Register Control Port supports the AXI4-Lite protocol with burst length always as 1 (that is, register-style interface).

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  • Supports First-Generation HyperRAM specifications
  • Supports up to two HyperRAM devices
  • HyperBus clock speed is up to 162 MHz only
  • Supports Single HyperBus Clock only
  • Uses two separate AXI-4 buses for Memory Control and Register Control