The Dual HiSPi Sensor Interface to Parallel ISP bridge is a reference design that allows two image sensors to be merged to a single ISP. There exists several applications in which two sensors are desired. A few examples include 3D video, precise factory automation control, black box car driver recorder, accurate analytics in security cameras, etc. In this design, two Aptina 9MT024/34 HiSPi sensors (720p) are input to a LatticeMachXO2 device. The LatticeMachXO2 deserializes the two sensor interfaces, and then combines the image with assistance of the LP SDRAM for frame buffering. The output is a parallel bus of the combined images so an ISP can process the stream. The LatticeMachXO2 is a low cost, non-volatile FPGA. Combined with the LP SDRAM, it provides an efficient and cost-effective solution for bridging two image sensors to an ISP.
The Dual HiSPi sensor reference design can be demonstrated on the Dual Sensor Interface Board (DSIB) with the use of the HDR-60 and two 9MT024 Nanovesta boards. See picture below for the demonstration setup. To order the DSIB, the part number is LCMXO2-4000HE-DSIB-EVN.
For details on the HDR-60 board and the 9MT024 Nanovesta sensor board, visit www.latticesemi.com/HDR60. For an overview of the dual sensor demo, download the Quick Start Guide for DSIB or EB69 DSIB eval board user guide.