1553 Encoder/Decoder

Reference Design LogoThe MIL-STD-1553 is a low-speed serial bus used in avionics systems. This reference design implements Manchester II encoding and decoding required by the 1553 along with synchronization pattern insertion and identi-fication, data serialization and de-serialization and parity checking and insertion functions.

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Block Diagram

1553 Encoder 1553 Decoder

Performance and Size

  Language Testbench Performance
Tested Device* Size Reported Frequency
Decoder Verilog Yes LFEC20E-4 53 SLICEs 8 MHz
Decoder Verilog Yes LFXP10E-4 53 SLICEs 8 MHz
Encoder Verilog Yes LFEC20E-4 39 SLICEs 2 MHz
Encoder Verilog Yes LFXP10E-4 39 SLICEs 2 MHz

* May work in other devices as well.

Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise. 


Technical Resources
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Encoder/Decoder - Source Code for LatticeXP
RD1021 4/1/2005 ZIP 472.7 KB
Encoder/Decoder - Source Code
RD1021 7/1/2004 ZIP 32.9 KB
Also download the ECP/EC source code and XP source code below
RD1021 7/1/2004 PDF 64 KB

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