MDIO Peripheral - WISHBONE Compatible

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This reference design implements an MDIO (Management Data Input/Output Interface) slave interface as specified in the IEEE 802.3 standard. The primary application of the peripheral is to provide a Serial Management Interface (SMI) to transfer management data between an Ethernet Media Access Controller (MAC) and a physical layer device (PHY).

Features

  • Implements the IEEE 802.3 Standard, Clause 22 interface
  • Support 16 registers, as defined in the IEEE 802.3 Standard, Clause 22
  • All registers can be read through the MDIO bus
  • All registers can be read through the WISHBONE bus
  • All R/Wa registers can be written through the MDIO bus
  • All ROb registers can be written through the WISHBONE bus
  • The slave PHY address can be set with the WISHBONE bus

Jump to

Block Diagram

MDIO-Wishbone

Performance and Size

Tested Devices* Performance I/O Pins Design Size Revision
LCMXO640C-4T100C >50 MHz 32 450 LUTs 1.1
LFE3-95EA-7FN1156C >150 MHz 32 450 LUTs 1.1

1 The Max. Clock Frequency is obtained by running the Timing Analysis of Lattice design software. Please run the timing simulation after you merge it with your design.

Documentation

Technical Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
MDIO Peripheral - WISHBONE Compatible - Source Code
RD1074 1.1 2/19/2010 ZIP 354.1 KB
MDIO (Management Data Input/Output Interface) Peripheral - WISHBONE Compatible
FPGA-RD-02130 1.2 1/31/2021 PDF 1021 KB

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