XIP8001B: True Random Number Generator (TRNG)

TRNG IP core including the NIST SP 800-90B startup and online health tests

The entropy source (“raw bits”) in XIP8001B has been extensively tested with PractRand, gjrand, TestU01, NIST SP 800-22 statistical test suite and the dieharder test suite.

Designed to comply with FIPS 140-3 standard.

Easy integration with other FPGA logic, as the functionality of XIP8001B does not rely on any FPGA family specific features.


  • Compact Size: The entire design requires only 2737 Lookup Tables (4LUTs) (Lattice ECP5) and 1-2 internal memory blocks in a typical FPGA implementation.
  • Autonomous Operation: The entropy source used by XIP8001B functions independently from the rest of the FPGA logic; for example no FPGA internal clock signals are required for the entropy source to function.
  • Standard Compliance: The core has been designed to comply with NIST SP 800-90B, thus making its use in a crypto module targeting a FIPS 140-3 certification possible.
  • Passing Statistical Tests: The output of the entropy source in XIP8001B passes PractRand, gjrand, TestU01, the NIST SP 800-22 statistical test suite, and the dieharder test suite.

Block Diagram

Internal high-level block diagram of XIP8001B

Resource Usage and Performance

FPGA family Resources Output bit rate
Lattice ECP5 2737 4LUTs, 3 EBR 2.79 Mbps

Resource usage and performance of XIP8001B on Lattice ECP5 FPGA family. On request, the resource estimates can also be supplied for other Lattice FPGA families.

Ordering Information

Please contact sales@xiphera.com for pricing and your preferred delivery method. XIP8001B can be shipped in a number of formats, including netlist, source code, or encrypted source code. Additionally, a comprehensive VHDL testbench and a detailed datasheet are included.

You can download the Lattice Product Brief from https://xiphera.com/partners/lattice/XIP8001B_PB_lattice.pdf


Information Resources
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Xiphera Lattice IP Core Metrics
1.0 8/5/2021 PDF 41.2 KB

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