The balanced TRNG from Xiphera is a True Random Number Generator (TRNG) Intellectual Property (IP) core designed in generic and portable VHDL. The output of the entropy source (the so-called “raw bits”) in the IP core have been successfully tested with PractRand, gjrand, TestU01, NIST SP 800-22 statistical test suite and the dieharder test suite.
Standard Compliance: The core has been designed to comply with NIST SP 800-90B, thus making its use in a crypto module targeting a FIPS 140-3 certification possible.
Autonomous Operation: The entropy source used by the IP core functions independently from the rest of the FPGA logic; for example, no FPGA internal clock signals are required for the entropy source to function.
Parameterizability: The balanced TRNG IP core has a number of parameterizable features, including the width of the dout output, the sizes (width and depth) of the internal buffers, and the threshold values for the health tests.
Compact Size: The entire design requires only 3063 Lookup Tables (4LUTs) (Lattice® ECP5®) and 1-2 internal memory blocks in a typical FPGA implementation.
Passing Statistical Tests: The output of the entropy source in the IP core passes PractRand, gjrand, TestU01, the NIST SP 800-22 statistical test suite, and the dieharder test suite.