XIP4001C: X25519

Very compact IP core designed for efficient key exchange using the X25519 protocol

Related Products

XIP4001C calculates the operation Qx= s * Px using the Montgomery Ladder Algorithm, where Px is the 255 bits long input argument, s is the 256 bits long secret key and Qx is the 255 bits long point multiplication result.

Easy integration with other FPGA logic, as the functionality of XIP4001C does not rely on any FPGA family specific features.

Features

  • Minimal Resource Requirements: The entire XIP4001C requires less than 1k Logic Elements and uses only 1-2 multipliers/DSP Blocks 2 and one memory block in a typical FPGA implementation.
  • Constant Latency: The execution time of XIP4001C is independent of the key value, and consequently provides protection against timing-based side-channel attacks.
  • Performance: Despite its small size, XIP4001C can support more than 100 key exchange operations per second.
  • Standard Compliance: XIP4001C is compliant with RFC 7748, and can be used in many public-key protocols including IKEv2 (RFC 8031) and TLS 1.3 (RFC 8446).

Block Diagram

Internal high-level block diagram of XIP4001CExpand Image

Resource Usage and Performance

FPGA family Resources Output bit rate
Lattice ECP5 1003 4LUTs, 1 EBR, 1 MULT18 160.43 MHz

Resource usage and performance of XIP3034H on Lattice ECP5 FPGA family. On request, the resource estimates can also be supplied for other Lattice FPGA families.

Ordering Information

Please contact sales@xiphera.com for pricing and your preferred delivery method. XIP4001C can be shipped in a number of formats, including netlist, source code, or encrypted source code. Additionally, a comprehensive VHDL testbench and a detailed datasheet are included.

You can download the Lattice Product Brief from https://xiphera.com/partners/lattice/XIP4001C_PB_lattice.pdf

Documentation

Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
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Xiphera Lattice IP Core Metrics
1.0 8/5/2021 PDF 41.2 KB

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