AES256-XTS, Balanced (XIP1183B)

XIP1123B – Balanced AES (256-bit key), ECB, CBC, OFB, CFB, and CTR Mode of Operation

The balanced AES-XTS Intellectual Property (IP) core implements the Advanced Encryption Standard (AES) with 256 bits long key in XTS mode. AES-XTS is block-oriented cipher used primarily for protecting the confidentiality of data at rest. Consequently, AES-XTS is widely used for encrypting the contents of hard drives and other storage devices.

Standard Compliance: The balanced AES-XTS IP core is compliant with both the Advanced Encryption Algorithm (AES) standard, and the XTS standard.

Optional Ciphertext stealing support as defined in IEEE Std. 1619-2018. Increased Performance can be achieved by parallel instantiations of the IP core.

Moderate resource requirements: The entire IP core requires 19326 4-input Lookup Tables (4LUTs) (Lattice CertusPro-NX®), and does not require any multipliers or DSPBlocks.

Performance: The IP core achieves an impressive throughput in the Gbps range, for example 793.58+ Gbps in Lattice CertusPro-NX.

Block Diagram

Internal high-level block diagram of Xiphera’s balanced AES-XTS IP core

Ordering Information

Please contact for pricing and your preferred delivery method. The IP core can be shipped in a number of formats, including netlist, source code, or encrypted source code. Additionally, a comprehensive VHDL testbench and a detailed datasheet are included.

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