XIP1113B: AES256-GCM Balanced IP Core

Balanced IP core implementing AES-256 in GCM mode of operation

Related Products

AES Galois Counter Mode (GCM) is a popular Authenticated Encryption with Associated Data (AEAD) cipher and its example use cases include securing TLS traffic.

Easy integration with other FPGA logic, as the functionality of XIP1113B does not rely on any FPGA family specific features.

Features

  • Compact resource requirements: The entire XIP1113B requires 6134 Lookup Tables (4LUTs) (Lattice ECP5), and does not require any multipliers, DSPBlocks or internal memory in a typical FPGA implementation.
  • Performance: Despite its compact size, XIP1113B achieves a throughput in the Gbps range, for example 1.08+ Gbps in Lattice ECP5.
  • Standard Compliance: XIP1113B is fully compliant with both the Advanced Encryption Algorithm (AES) standard FIPS-197 as well as with the Galois Counter Mode (GCM) standard SP 800-38D.

Block Diagram

Internal high-level block diagram of XIP1113BExpand Image

Resource Usage and Performance

FPGA family Resources fMAX Max. Throughput
Lattice ECP5 6134 4LUTs 117.69 MHz 1.08 Gbps

Resource usage and performance of XIP1113B on Lattice ECP5 FPGA family. On request, the resource estimates can also be supplied for other Lattice FPGA families.

Ordering Information

Please contact sales@xiphera.com for pricing and your preferred delivery method. XIP1113B can be shipped in a number of formats, including netlist, source code, or encrypted source code. Additionally, a comprehensive VHDL testbench and a detailed datasheet are included.

You can download the Lattice Product Brief from https://xiphera.com/partners/lattice/XIP1113B_PB_lattice.pdf

Documentation

Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
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Xiphera Lattice IP Core Metrics
1.0 8/5/2021 PDF 41.2 KB

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