Watchdog Timer IP Core

The Watchdog Timer IP Core is designed for use as an indicator that a corrective action is needed in response to a computer or a processor malfunction. The design features a two-stage timer which supports non-maskable interrupt and a hard reset.

Features

  • Seamlessly work with sleep mode
  • Programmable timer spec 50-500 ms (10 ms)
  • Two-stage timer that supports warm boot and cold boot resets
  • You can specify in cycles or time
  • Supports trigger input, reset and NMI output

Jump to

Block Diagram

Performance and Size

Resource Utilization
Configuration Clk Fmax (MHz) Slice Registers LUTs EBRs
Default 175.840MHz 52 116 0
Timer Stage 1 Timeout = 1050, Others = Default 200MHz 52 117 0
Mode Time, Clock Frequency = 150, Others = Default 189.107 52 128 0
Mode Time, Timer Stage 2 Timeout = 100, Others = Default 160.154MHz 2 126 0

Ordering Information

The Watchdog Timer IP Core is available for free to use in Lattice Radiant design software.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Watchdog Timer IP Core - Lattice Radiant Software
FPGA-IPUG-02097 1.3 6/23/2021 PDF 936 KB

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