I2C Master IP Core

Control for I2C Bus Interface

I2C I2C (Inter-Integrated Circuit) bus is a simple, low-bandwidth, short-distance protocol. It is often seen in systems with peripheral devices that are accessed intermittently. It is commonly used in short-distance systems, where the number of traces on the board should be minimized. The device that initiates the transmission on the I2C bus is commonly known as the Master, while the device being addressed is called the Slave.

Lattice Semiconductor general-purpose I2C Master IP Core offers an effective way to control an I2C bus. The programmable nature of FPGA provides users with flexibility of configuring the I2C Master device to their needs, thus allowing users to customize the I2C Master Controller to meet their specific design requirements.

This design is implemented in Verilog. It can be targeted to CrossLink-NX™ FPGA devices and implemented using the Lattice Radiant Software Place and Route tool integrated with the Synplify Pro® synthesis tool.

Features

  • Supports 7-bit and 10-bit Addressing Mode with Programmable SCL frequency, supporting the bus speeds: Standard-mode (Sm) – up to 100 kbit/s, Fast-mode (Fm) – up to 400 kbit/s and Fast-mode Plus (Fm+) – up to 1 Mbit/s
  • Integrated Pull-up and Glitch filter
  • Arbitration lost detection in multi-master system
  • Polling and Out-of-band Interrupt Modes
  • Selectable LMMI or APB interface supports Clock stretching

Block Diagram

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
I2C Master IP Core - Lattice Radiant Software
FPGA-IPUG-02071 1.2 6/24/2020 PDF 1.3 MB

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