QDRII + SRAM Controller MACO Core


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IP ExpressThe second generation Quad-Data-Rate (QDRII) Static Random Access Memory (SRAM) Controller is a general purpose memory controller that interfaces with industry standard QDRII and QDRII+ SRAM. The controller can be configured to function in two-word burst or four-word burst modes. It can also be configured to have an 18-bit bus or a 36-bit data bus. The data is transferred on both edges of the clock, doubling the rate of data transfer. Separate read and write data buses again double the data rate.

MACOThe QDRII+ IP Core is implemented using both MACO ASIC gates and soft logic in the FPGA array. Since a significant portion of the implementation is in MACO, more of the FPGA Array is left for the user.

Software Requirements

  • ispLEVER version 7.0 or later
  • MACO design kit
  • MACO license file

Features

  • Interfaces to industry standard QDRII or QDRII+ SRAM
  • Supports QDRII SRAM memory devices operating up to 250MHz
  • Supports QDRII+ SRAM memory devices operating up to 375MHz (highest speed grade)
  • FPGA can be configured for 18-bit or 36-bit read and write memory data buses (on FPGA, 36-bit or 72-bit data buses)
  • Shared address bus can be configured from 17 bits to 20 bits wide
  • Programmable burst lengths of two or four
  • Maximum read/write blocks of 31 consecutive locations

Jump to

Block Diagram

QDRII Controller Block Diagram

Performance and Size

Results for LatticeSCM
Configuration SLICEs LUTs Regs PIOs
Type Data Width Address Width Mem Speed2
(MHz)		 R/W FIFO Depth Latency Burst Mode
QDRII+ 18 18 3002 4 / 4 2.5 4 230 297 233 194
QDRII+ 36 18 3002 4 / 4 2.0 4 342 406 382 194
QDRII 18 18 2502 64 / 64 1.5 2 453 717 242 194

1) Performance and utilization characteristics are generated using Lattice's ispLEVER® v7.0 software. When using this IP core with different software or in a different speed grade, performance may vary. Not all configurations will fit on smaller LatticeSCM devices. These results are from Synplify v8.8L2.

2) Performance results for -5 speed grade.

Ordering Information

Licensing

All MACO IP is free of charge. However a license key is required to enable simulation and bitstream generation. Please contact your local Lattice Sales Office to obtain your MACO IP license key.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
QDRII+ SRAM Controller MACO Core User Guide
IPUG45 01.4 3/12/2008 PDF 831.6 KB

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