EP201: PowerPC Bus Master

The PowerPC bus master is a bus interface unit designed for the PowerPC host bus. It allows the user to initiate data transfer directly on the PowerPC CPU bus through a very simple user interface.

The PowerPC bus master arbitrates for the PowerPC address bus before starting any transfers. It handles separate address and data bus tenure so that data bus is arbitrated independently from the address bus. The bus master handles address retry by the CPU or other sources on the CPU bus. Upon address retry, it automatically re-starts the data transfer unless an error has occurred.

Single beat, burst data and extended MPC8260 data transfer are supported. Different data size and transfer types are allowed and can be specified through an internal back-end bus. There are two user interface ports provided by the bus master. It allows two different devices to access the PowerPC bus through a single bus master. The bus master contains arbitration logic to arbitrate between the two request ports.

Features

  • Fully supports PowerPC™ 60x bus protocol, include PowerPC 603, 604, 740, 750 and 8260.
  • Automatic bus arbitration for address bus and data bus based on internal bus request.
  • Separate address bus and data bus tenure with individual grant signals.
  • Supports address bus retry and data transfer error.
  • Qualified address bus grant and data bus grant through the use of bus busy signals.
  • User specified burst data transfer and single beat data transfer.
  • Supports two back-end user request ports with built-in arbitration.
  • Efficient back-end bus for internal data transfer.
  • Supports bus parking.
  • Designed for ASIC or programmable logic device implementations in various system environments.
  • Fully static design with edge triggered flip-flops.
  • Optimized for ispXPGA product family.

Jump to

Block Diagram

Performance and Size

The following are typical performance and utilization results.

Lattice Device Utilization Performance
PFUs Slices LUTs Percentage
LFX1200B 133 4% 94Mhz
LFFC20 527 4% 115Mhz
LFXP10 431 8% 115Mhz
LFXP2-17E 298 4% 143Mhz

Ordering Information

This IP core is supported and sold by Eureka Technology, contact Eureka Technology at info@eurekatech.com or visit their website at www.eurekatech.com for more information.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
PowerPC Bus Master Datasheet
EP201 6/22/2007 PDF 91.6 KB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.

Like most websites, we use cookies and similar technologies to enhance your user experience. We also allow third parties to place cookies on our website. By continuing to use this website you consent to the use of cookies as described in our Cookie Policy.