DSPI: Serial Peripheral Interface - Master/Slave

DCD LogoThe DSPI is a fully configurable SPI master/ slave device, which allows user to configure polarity and phase of serial clock signal SCK.

The DSPI allows the microcontroller to communicate with serial peripheral devices. It is also capable of interprocessor communications in a multi-master system. A serial clock line (SCK) synchronizes shifting and sampling of the information on the two independent serial data lines. DSPI data are simultaneously transmitted and received.

The DSPI is a technology independent design that can be implemented in a variety of process technologies.

The DSPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. The system can be configured as a master or a slave device. Data rates as high as CLK/4. Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects one of four different bit rates for the serial clock.

The DSPI automatically drive selected by SSCR (Slave Select Control Register) slave select outputs (SS7O . SS0O), and address SPI slave device to exchange serially shifted data. Error-detection logic is included to support interprocessor communications. A write-collision detector indicates when an attempt is made to write data to the serial shift register while a transfer is in progress. A multiple-master mode-fault detector automatically disables DSPI output drivers if more than one SPI devices simultaneously attempts to become bus master.

DSPI is fully customizable, which means it is delivered in the exact configuration to meet users' requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.


SPI Master

  • Master and Multi-master operations
  • 8 SPI slave select lines
  • System error detection
    • Mode fault error
    • Write collision error
  • Interrupt generation
  • Supports speeds up of system clock
  • Bit rates generated 1/4, 1/8, 1/ 16, 1/32 of system clock.
  • Four transfer formats supported
  • Simple interface allows easy connection to microcontrollers

SPI Slave

  • Slave operation
  • System error detection
  • Interrupt generation
  • Supports speeds up 1/4 of system clock
  • Simple interface allows easy connection to microcontrollers
  • Four transfer formats supported

Fully synthesizable, static synchronous design with no internal tri-states


  • Embedded microprocessor boards
  • Consumer and professional audio/video
  • Home and automotive radio
  • Digital multimeters

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Block Diagram

Performance and Size

Device Speed grade LUTs/PFUs Fmax
SC -7 162/84 337 MHz
ECP2 -7 167/84 279 MHz
ECP2M -7 167/84 279 MHz
XP -5 175/89 179 MHz
XP2 -7 146/93 221 MHz
EC/ECP -5 175/89 187 MHz
ispXPGA -5 137/40 164 MHz
ORCA 4 -3 160/26 121 MHz
ORCA 3 -7 150/26 75 MHz

Ordering Information

This IP core is supported and sold by DCD, contact DCD at support@dcd.pl or visit their website at www.dcd.pl for more information.


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DCD: DSPI: Serial Peripheral Interface - Master/Slave
2.08 6/22/2007 PDF 149.5 KB

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