DRPIC1655X: High Performance Configurable 8-bit RISC MCU

DCD LogoThe DRPIC1655X is a low-cost, high performance, 8-bit, fully static soft IP Core, dedicated for operation with fast (typically on-chip) dual ported memory. The core has been designed with a special concern about low power consumption.

DRPIC1655X soft core is software-compatible with the industry standard PIC16C554 and PIC16C558. It implements an enhanced Harvard architecture (i.e. separate instruction and data memories) with independent address and data buses. The 14 bit program memory and 8-bit dual port data memory allow instruction fetch and data operations to occur simultaneously. The advantage of this architecture is that instruction fetch and memory transfers can be overlapped by multi stage pipeline, so that the next instruction can be fetched from program memory while the current instruction is executed with data from the data memory.

The DRPIC1655X architecture is 4 times faster compared to standard architecture. So most instructions are executed within 1 system clock period, except the instructions which directly operates on program counter PC (GOTO, CALL, RETURN), this situation require the pipeline to be cleared and subsequently refilled. This operation takes additional one clock cycle.

The DRPIC1655X Microcontroller fits perfectly in applications ranging from high-speed automotive and appliance motor control to low-power remote transmitters/receivers, pointing devices and telecom processors. Built-in power save mode make this IP perfect for applications where power consumption is critical.

DRPIC1655X is delivered with fully automated testbench and complete set of tests allowing easy package validation at each stage of SoC design flow.


  • Software compatible with industry standard PIC16C55X
  • Pipelined Harvard architecture 4 times faster compared to original implementation
  • 35 instructions
  • 14 bit wide instruction word
  • Up to 512 bytes of internal Data Memory
  • Up to 64K bytes of Program Memory
  • Configurable hardware stack
  • Power saving SLEEP mode
  • Fully synthesizable, static synchronous design with no internal tri-states
  • Scan test ready
  • Technology independent HDL Source Code
  • 800 MHz virtual clock frequency in a 0.35u technological process

Jump to

Block Diagram

Performance and Size

Device Speed grade Fmax LUTs PFUs
XP -5 78 MHz 757 307
ECP -5 85 MHz 757 307
EC -5 85 MHz 757 307
ORCA 4E -3 50 MHz 733 122

Ordering Information

This IP core is supported and sold by DCD, contact DCD at support@dcd.pl or visit their website at www.dcd.pl for more information.