The fleximac_sys_xge module contains both the flexiPCS instantiation and the flexiMAC user defined module (contains FLXMC MACO + FIFOs).
You can remove the flexiPCS block from the fleximac_sys_xge as long as you tie off the flexiPCS output connections to other existing logic. In addition you must create a testbench capable of transmitting/receiving XGMII packets to/from the flexiMAC.
It is your responsibility to develop the XGMII packet generator in the testbench, or add your own PCS model in the testbench, as the existing testbench does not include such an element.
Here are the XGMII signals defined in the
fleximac_sys_xge that you need to bring out to your testbench level:
- ref_pclk (source clock for XGMII data) : input from testbench
- tphy_txd_0[7:0] through tphy_txd_3[7:0] (XGMII TX data) : output to testbench
- tphy_txc_0 through tphy_txc_3 (XGMII TX control) : output to testbench
- rphy_rxd_0[7:0] through rphy_rxd_3[7:0] (XGMII RX data) : input from testbench
- rphy_rxc_0 through rphy_rxc_3 (XGMII RX control) : input from testbench