The only way to preserve (even names) those net/signals into your netlist is through the utilization of the Synthesis Attributes.
Unfortunately, there is no additional feature for preventing optimization.
You can use the following:
1) syn_keep on a wire/register (Verilog) or signal (VHDL) to preserve the net for simulation, a different synthesis implementation, or for passing to the PAR tool. It can also preserve duplicate driver cells and prevent it from sharing.
2) syn_probe on a wire/register (Verilog) or signal (VHDL) to preserve the internal net for probing
3) syn_preserve on a module/register (Verilog) or signal or architecture (VHDL) to preserve the logic of constant-driven registers, registers for simulation, prevents sharing, and sequential components. This also helps preserve state machines.
4) syn_noprune on module/component (Verilog) or architecture/instance (VHDL) to preserve instantiated components.