Description:
When running simulation wizard directly on a design which includes a PLL, a fatal error is encountered as given below
** Fatal: (vsim-3693) The minimum time resolution limit (10fs) in the Verilog source is smaller than the one chosen for SystemC or VHDL units in the design. Use the vsim -t option to specify the desired resolution.
# FATAL ERROR while loading design
Solution:
Unfortunately, when running a simulation using the Simulation wizard, the tool is not capable of identifying the required minimum resolution from your design (this is a tool limitation). To overcome this error, you should manually change the resolution of your simulation, you can do this by performing the following:
1) Compile > Compile All
Result:
2) Simulate > Start Simulation > Select your testbench under Work > Select Resolution > OK
With this, you should be able to run add signals and run your simulation.