Follow these recommendations to generate several clock signal outputs with minimum jitter:
1. Use the PLL and the ODDR clocked by the edge clock.
2. Use a clock source with less jitter.
3. Use dedicated clock input routing pins to assign the clock to the device.
4. Avoid any local routing.
5. Use I/O Register for the output, this should improve the jitter spec.
6. Have virtual/pseudo ground around the output pin to isolate the signal.