Yes, it is possible. Following is an example of using DSP block to implement function of MUX 16 to 1:
Verilog:
integer i;
always @(sel)
for (i=0;i<16;i=i+1) begin
sel_one_hot[i] = sel == (15 - i);
end
mult_16_16 I_mult_16_16 (.A (sel_one_hot), .B (D), .P (P)); //using IP express to generate 16*16 DSP module
assign Z = P[16];
VHDL:
sel_one_hot <= "1000000000000000" when sel == "0000" else "0100000000000000" when sel == "0001" else "0010000000000000" when sel == "0010" else "0001000000000000" when sel == "0011" else "0000100000000000" when sel == "0100" else "0000010000000000" when sel == "0101" else "0000001000000000" when sel == "0110" else "0000000100000000" when sel == "0111" else "0000000010000000" when sel == "1000" else "0000000001000000" when sel == "1001" else "0000000000100000" when sel == "1010" else "0000000000010000" when sel == "1011" else "0000000000001000" when sel == "1100" else "0000000000000100" when sel == "1101" else "0000000000000010" when sel == "1110" else "0000000000000001" when sel == "1111";I_mult_16_16 : mult_16_16 port map(A=> sel_one_hot, B => D, P => P);
Z <= P(16);