There are several reasons why users will see this happen:
- The timing constraint specified is covered by another timing constraint in the preference file. This is most often seen when the design has two related clocks. Trace will provide timing information for one of the clocks using timing constraint information for the other clock domain. User can see how Trace relates the clocks at the bottom of the report.
- The clock has been optimized out or renamed. Check the HDL synthesis tool's reports to see if the clock or associated logic has been removed.
- The clock is used only for I/O that has a fixed timing path. This negates the need for a frequency preference. Instead, a "Clock to Out" or "Input Setup" constraint should be used.