All Devices: When the input clock to the LatticeFPGA PLL is a Spread Spectrum Clock (SSC), does the SSC pass through the PLL, or is it filtered by the PLL?
The PLL passes the SSC input to the output because the SSC modulation frequency is far below the PLL's bandwidth (2-4 MHz). This answer specifically applies to industrial standard Spread Spectrum Clocking with a modulation rate between 30 kHz and 33 kHz, and a modulation frequency range of 0 to -0.5%.