When using the DDR IO register (Double Date Rate) in a LatticeECP3 design, a user must implement a dedicated clock route for the clock being used at the DDR registers.
For an aligned interface using a DLL/PLL (Delay Locked Loop/ Phase Locked Loop) to shift the input clock, the clock input must be assigned to a dedicated DLL/PLL input pin. If using a PCLK pin instead, then the user must implement a "USE PRIMARY" preference so that the clock is routed to a primary clock tree.
For a centered interface that is not using a PLL/DLL instead the clock is directly routed to primary/edge clock tree going to DDR registers, then the clock must be assigned to a PCLK pin.
You can refer to section "High Speed DDR Interface Details" in
TN1180 - LatticeECP3 High Speed I/O Interface for more details on each type of DDR interface.