SPI Slave Controller Reference Design

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Reference Design LogoThe Serial Peripheral Interface (SPI) is used primarily for synchronous serial communication between a host processor and its peripherals. The SPI bus is often selected because of its low pin count and full-duplex mode that can achieve data throughput in the tens of Mbps range. The SPI bus uses a 4-wire interface with two unidirectional data lines to communicate between the master and the selected slave. It supports one master with multiple slaves on one bus and allows protocol flexibility for the bit transferred.

This reference design implements a SPI slave device interface that provides full-duplex, synchronous, serial communication with the SPI master. The data size of the SPI bus can be configured to either 16 or 8 bits. The SPI Slave Controller reference design supports all modes of CPOL and CPHA – 00, 01, 10 and 11.

This design uses three pins (clock, data in and data out) plus one select for each slave device. A SPI is a good choice for communicating with low-speed devices that are accessed intermittently and transfer data streams rather than reading and writing to specific addresses. A SPI is an especially good choice if we can take advantage of its full-duplex capability for sending and receiving data at the same time.

This design is implemented in VHDL. The Lattice iCECube2™ Place and Route tool integrated with Synplify Pro synthesis tool is used for the implementation of the design. The design uses an iCE40™ ultra low density FPGA and can be targeted to other iCE40 family members.


  • Supports all four modes of CPOL and CPHA operation (00/01/10/11)
  • Supports variable data widths (8 and 16 bits)
  • Provision for easy integration of any processor interface
  • IP-XACT version 1.2 compliant

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Block Diagram

SPI Slave Controller Block Diagram

Performance and Size

Device Family Utilization (LUTs) Language fMAX (MHz) I/O Pins Architectural
iCE40™ 217 VHDL 254 48 N/A

Performance and resource utilization characteristics are generated using iCE-40LP1K-CM121 with iCEcube2 design software.

Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.


Technical Resources
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SPI Slave Controller - Source Code
RD1142 1.1 1/12/2015 ZIP 377.1 KB
SPI Slave Controller - Documentation
RD1142 1.0 10/12/2012 PDF 667.2 KB

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