The Serial Peripheral Interface (SPI) is used primarily for synchronous serial communication between a host processor and its peripherals. The SPI bus is often selected because of its low pin count and full-duplex mode that can achieve data throughput in the tens of Mbps range. The SPI bus uses a 4-wire interface with two unidirectional data lines to communicate between the master and the selected slave. It supports one master with multiple slaves on one bus and allows protocol flexibility for the bit transferred.
This reference design implements a SPI slave device interface that provides full-duplex, synchronous, serial communication with the SPI master. The data size of the SPI bus can be configured to either 16 or 8 bits. The SPI Slave Controller reference design supports all modes of CPOL and CPHA – 00, 01, 10 and 11.
This design uses three pins (clock, data in and data out) plus one select for each slave device. A SPI is a good choice for communicating with low-speed devices that are accessed intermittently and transfer data streams rather than reading and writing to specific addresses. A SPI is an especially good choice if we can take advantage of its full-duplex capability for sending and receiving data at the same time.
This design is implemented in VHDL. The Lattice iCECube2™ Place and Route tool integrated with Synplify Pro synthesis tool is used for the implementation of the design. The design uses an iCE40™ ultra low density FPGA and can be targeted to other iCE40 family members.