Lattice Blog


Lattice Certus-NX: Reinventing the Low Power, General Purpose FPGA

Certus-NX Blog
Posted 06/24/2020 by Juju Joyce

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Last December, we announced our new low power FPGA development platform, Lattice Nexus™, the first low power FPGA platform to use a 28 nm FD-SOI manufacturing process. Nexus uses innovations at every level of design - from software solutions, to the fabric architecture, and all the way down to the individual circuits - to deliver higher system performance at significantly reduced power consumption. The first device developed on Lattice Nexus, CrossLink™-NX, is a specialized FPGA with a feature set created to support smart and embedded vision applications.

Now, just six months after the launch of CrossLink-NX, Lattice is reinventing the low power, general-purpose FPGA by applying benefits of the Nexus platform to a new family of devices, Lattice Certus™-NX. These FPGAs provide strong data co-processing, signal bridging, and system control capabilities for use in a broad range of applications, including industrial, automotive, communications, and compute.

Introducing Certus-NX

Certus-NX FPGAs deliver up to twice the I/O density per mm2 of similar competing FPGAs. By placing such high I/O density in a small form factor, customers can easily incorporate a Certus-NX FPGA into a new or existing system design without significant impact on the design footprint. This makes many application options possible, and we look forward to seeing the creative ways our customers implement Certus-NX in their applications.

Why Certus-NX?

Technology trends like industrial automation and 5G have developers looking to add processing and connectivity to applications that operate across the network, from the datacenter to the Edge. But that data needs to be processed and moved between chips and systems, and that data processing and connectivity must be implemented in ways that don’t add to overall system power consumption and size. These components also need to be highly reliable and secure, particularly when used in mission- or safety-critical equipment (i.e. industrial robots, ADAS, 5G infrastructure).

Certus-NX - Processing Trends

Successfully supporting these technologies requires customers build their systems using hardware components that perform well in the following areas.

  • Low power operation to keep power consumption and thermal budgets under control
  • Small size so adding components to a design to enable a new application doesn’t impact the design footprint
  • Strong support for PCI Express (PCIe) and Gigabit Ethernet, the I/O standards that commonly handle data moving chip-to-chip in a system
  • Highly reliable operation to keep mission- and safety-critical systems up and running
  • Security features that protect the device from running unauthorized firmware and keep customer IP secured against cloning/copying

These were the considerations in mind when we developed Certus-NX, and we believe this new family of FPGAs really delivers on all of those points.

  • Thanks to the Nexus platform, Certus-NX uses up to 4x less power than FPGAs with similar features and logic densities
  • Manufactured in a 28 nm FD-SOI process, Certus-NX FPGAs are up to 3x smaller in size compared to competing devices
  • The devices offer up to 1.5 Gbps of differential I/O bandwidth, which is up to 70 percent higher than the competition. PCI Express throughput really stands out, thanks to a 5 Gbps PCIe IP core available for implementation on the devices.
  • To secure the FPGA bitstream against unauthorized access, Certus-NX FPGAs support AES-256 encryption with ECDSA authentication to protect devices throughout their lifecycles. This lets OEMs know their IP is secure from copying or cloning, and unauthorized firmware cannot be uploaded to the FPGA.
  • Certus-NX FPGAs are highly resistant to soft errors; up to 100 times higher than competing devices. Soft errors can disrupt normal system operation, a potentially dangerous situation for safety-critical applications. The devices also provide fast instant-on performance, which lets the FPGA reboot in just 3 ms, and allows the entire system to reset in only 8-14 ms, so if an error does occur, the system can reset in near real time.