When Map reports an error of the type
@E: BN245 :"c:\temp\c95734\video_pass_through.vhd":59:2:59:8|Port 'RCLK_in' on Chip 'Video_Pass_Through' drives 1 PAD loads and 482 non PAD loads
Process took 0h:00m:02s realtime, 0h:00m:02s cputime
The message basically says that an input to the design is going to both the input pin of an input buffer as well as to other FPGA logic.
Software design flow does not allow sharing inputs to input buffers with other logic. The input port has to be dedicated to the buffer input pin.