Solution:
1. Defining the usr_lmmi_offset_i [16:2]
a. usr_lmmi_offset_i [16] == selects between Link Layer or PHY register access
b. usr_lmmi_offset [15:2] == refer to FPGA-IPUG-02126 \u00E0 word aligned offset of base + offset address
2. Write \u201C1'b0\u201D on usr_lmmi_offset_i [16] to select Link Layer register access.
3. As an example, write \u201C408C\u201D on usr_lmmi_offset_i [15:2] to select the offset address of pcie_link_stat Register.
a. mgm_ftl base address = 0x4000
b. reg_byte_offset [15:0] = 0x408C
c. usr_lmmi_offset_i [16:2] = {1'b0, reg_byte_offset [15:2]}
4. Then, the user can now write the bit of the register in usr_lmmi_wdata_i [31:0].
a. For example the bit 12 of register 8C, usr_lmmi_wdata_i [12] = 1'b1 or 1'b0
Note: You can refer to the PCIe Demo for the sample LMMI App transaction.