DDR2: How to connect the terminations for address, control and data lines for Double Data Rate (DDR2)?
Usually the series terminations is close to the source and parallel is close to the destination.
For the address and control lines, the series terminations should be close to FPGA or the parallel close to memory. But for the bidirectional data lines, On Die Termination (ODT) is used to implement this function: during writing, the ODT in the memory is open, during reading, the ODT in the FPGA should be open.
Since the ODT in our device is not available, we usually connect the parallel terminations to Terminating Voltage (VTT) on data lines which are close to FPGA, and it is better than use series terminations that is close to memory during reading.