The LatticeECP2/M and LatticeECP3 Physical Coding Sublayer block (PCS) provides several protocol specific channel alignment state machines. It is possible to disable these protocol specific state machines. To permit the creation of an External Link State Machine (ELSM) the FPGA's PCS must be in 8b10b mode, and the CHx_COMMA_ALIGN control must be set to DYNAMIC.
When the protocol specific Link State Machines are bypassed the word aligner will begin comparing the incoming serial data against user-defined alignment character values. These values are specified during the PCS configuration in IP Express.
The Word Aligner (WA) must be primed to begin comparisons by the deassertion of the ffc_enable_cgalign_ch(0-3) control for a single clock clock period. The ffc_enable_cgalign_ch(0-3) is an active high control, and only needs to be desasserted for a single clock period to re-arm the WA. The WA in the PCS scans the incoming data stream and locks, i.e. quits performing comparisons, on the first successful character match. The WA remains locked until another ffc_enable_cgalign_ch(0-3) deassertion. A custom protocol External Link State Machine can be constructed by watching for the WA to lock, performing a compare against the character matched, and the re-arming of the WA using ffc_enable_cgalign_ch(0-3).