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ID: 204
Case Type: faq
Category: Architecture
Related To: General Logic
Family: All FPGA

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What is the initial logic level of a register after power-up?

We will consider two cases: (1) the control (reset, set) and clock signals are active upon device power-up and (2) the control and clock signals are in-active upon power-up. 

In the first case, the register's output will be determined by the logic driving the control and the data-in signals.

In the second case, the internally generated power-on-reset (POR) holds all the registers in an inactive mode until all the device power supplies (VCC, VCCAUX and VCCIOs) have reached satisfactory levels for the device to commence operation.  Thus, all the registers' outputs will have their fixed initial logic levels if their control signals are not active (e.g. no clock toggling) upon power-up. As for their initial logic levels, they depend on the configuration, i.e. settings of "RESET" or "SET". The "RESET" or "SET" setting is determined by the design logic. They can be asynchronous or synchronous. If "RESET" is selected, the register's initial output value is 0 or low. If "SET" is selected, the register's initial  output value is 1 or high. In the case where a register uses no asynchronous/synchronous set or reset controls, the "RESET" option is set by default.  The "RESET" and "SET" settings for all registers in your design can be found using the EPIC sofware tool.