The MachXO2 has 2 hardened SPI cores tied to the internal FPGA configuration logic. These cores can be accessed through an internal bus interface (wishbone) by instantiating the Embedded Function Block (EFB) element in HDL code.
The SPI cores have a hardened architecture inside the EFB and specific external configuration pins are required to be tied to the SPI cores. The spi_clk pin for the hardened SPI IP core is routed to CCLK/MCLK pin, which is the dedicated configuration clock port for the SPI programming port.
Further information on the SPI ports can be located in
TN1205, in the "Hardened SPI IP Core" section.